Digital Design Engineer - Mid or Senior Level

Digital Design Engineer - Mid or Senior Level

We are partnered with a deep tech semiconductor start up who specialize in developing high-performance, ultra-low-power data converter IP (Digital-to-Analog and Analog-to-Digital transceivers) for next-generation wireless communication systems like 5G‑Advanced and 6G. They are seeking a Digital Design Engineer with expertise in frontend RTL design and backend physical implementation to play a key role in developing high-performance digital and mixed-signal ICs in advanced technology nodes such as 22FDX, FinFET, and FD‑SOI processes.

Key Responsibilities

• Frontend RTL Design : Define micro‑architecture and implement digital subsystems (DSP blocks, control logic, interfaces).
• Backend Physical Implementation : Drive synthesis, floorplanning, place‑and‑route, clock tree synthesis, timing closure, and signoff (STA, LVS, DRC).
• Perform logic synthesis and collaborate with physical design teams to ensure smooth integration across digital and mixed‑signal boundaries.
• Support integration of digital IP with analog/mixed‑signal blocks.
• Contribute to testbenches, documentation, and post‑silicon bring‑up/debug.
• Senior‑level : Lead block‑level architecture, mentor junior engineers, and influence design methodology decisions.

Your Profile

• Strong proficiency in SystemVerilog/VHDL for RTL design, verification, and scripting (Python, Tcl, etc.).
• Experience with EDA toolchains from Cadence, Synopsys, or Mentor for synthesis, STA, and backend flows.
• Knowledge of low‑power design, clock domain crossing (CDC), and hierarchical SoC design.
• Hands‑on skills in physical implementation (floorplanning, P&R, CTS, STA, DRC, LVS).
• Familiarity with advanced nodes (22FDX, 16/12nm FinFET, or similar).
• Understanding of mixed‑signal integration, SoC assembly, and DFT concepts (a plus).
• Strong analytical and troubleshooting skills with attention to detail.

Qualifications

• Mid‑Level : 3–5 years of experience in digital IC design.
• Senior‑Level : 6+ years with proven ownership of IP/SoC blocks or backend flows.
• MSc or PhD in Electrical Engineering, Microelectronics, or related field.

On Offer

• A technically challenging role at the forefront of semiconductor innovation.
• Work on next‑generation data converter ICs and wireless communication systems.
• Competitive compensation, including salary and equity (VESOP).
• A dynamic, international team culture that encourages ownership and innovation.
• Flexible working arrangements focused on outcomes, not office hours.

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