About Aalyria:

Aalyria is a leading technology company that supplies laser communications technology and temporospatial software‑defined networking platforms to the aerospace industry. With technology acquired from Google, Aalyria is at the forefront of innovation in satellite and airborne mesh networks, as well as cislunar and deep‑space communications. We are revolutionizing the orchestration and management of planetary mesh networks using any radio or optical spectrum, any orbit, and any hardware across land, sea, air, and space.

Role Overview:

As the Lead RTL/FPGA Design Engineer on our Aalyria Space team, you will own the end to end the development of a high‑performance coherent modem targeting free space optical (FSO) communications. In this role, you'll own the RTL development of that modem from architecture through silicon bring‑up. That means translating complex DSP algorithms, equalization, carrier recovery, timing recovery, into clean, synthesizable RTL, integrating high‑throughput FEC engines, and ensuring the full design meets the demanding power, performance, and area targets required for a fielded aerospace system. You'll work directly alongside DSP algorithm developers and system architects, serving as the bridge between mathematical models and working hardware.

Key Responsibilities:

Deliver end‑to‑end FPGA Modem Solution based on VHDL or System Verilog.
Lead the micro‑architecture and RTL development for key digital signal processing (DSP) blocks in the coherent modem, including equalization, carrier recovery, and timing recovery.
Oversee the integration of Forward Error Correction (FEC) engines and high‑speed interfaces into the overall modem architecture.
Collaborate with system architects and DSP algorithm developers to translate DSP algorithm specification/models into robust RTL designs.
Design fixed‑point arithmetic RTL implementation of complex DSP blocks.
Ensure the design is compliant with relevant industry or company standards and specifications.
Apply low power design techniques and perform power, performance, and area (PPA) analysis.
Verify intended functionality using thorough test benches, and via vector matching with system models.
Behavioral modeling of complex digital blocks using HDL.
Support functional verification, debug, and static timing closure.
Collaborate closely with firmware/software engineers to define hardware/software partitioning, define registers and interfaces, and support system‑level integration and debug.
Support silicon bring‑up and bench testing.

Required Qualifications:

Active Security Clearance, or the eligibility to obtain one.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
5+ years of hands‑on experience in RTL design for high‑speed digital communications or related systems.
Proficiency in logic design concepts and high‑quality RTL coding using VHDL/SystemVerilog.
Proven experience in micro‑architecture definition and delivering detailed design specifications.
Demonstrated ability to ensure RTL designs are compliant with relevant industry or company standards and specifications.

Preferred Qualifications:

Prior experience delivering an end‑to‑end FPGA communication system solution (from architecture to successful hardware validation).
Deep expertise in implementing complex DSP functions in RTL, such as adaptive equalization, carrier recovery, and timing recovery.
Proven experience in the integration of high‑throughput FEC engines (e.g., LDPC, Reed‑Solomon) into a high‑speed data path.
Ability to convert system models (e.g., Matlab or C++) into robust fixed‑point RTL implementations, including successful vector matching and verification.
Familiarity with high‑speed FPGA synthesis, place and route (P&R), and static timing analysis (STA) flows.
Experience in designing for low power and high‑speed multi‑gigabit/sec interfaces.
Exposure to the MAC layer (Media Access Control) or digital interface layers adjacent to the PHY.
Experience with Python, Perl, TCL and/or other scripting languages.
Experience with SoC (System‑on‑Chip) architectures, including design integration and verification involving embedded processors (e.g., ARM).
Familiarity with defining and implementing hardware/software interface protocols for configuration and control.
Prior experience with coherent modem architectures or free space optical (FSO) communications systems is highly desired.

What We Offer:

Innovative Environment: Work at a cutting‑edge company shaping the future of aerospace communications.
Impactful Work: Directly contribute to critical national security programs and initiatives.
Growth Opportunities: Expand your career with opportunities for professional development and advancement.
Inclusive Culture: Be part of a collaborative, supportive, and inclusive workplace where your contributions matter.
Flexibility: Flexible working arrangements including hybrid remote/in‑office schedules.
Compensation and Equity: Competitive salary, comprehensive benefits (401(k), dental, vision, health, life insurance), paid time off, and equity options.

ITAR/EAR Requirements:

This position involves access to export‑controlled information. To comply with U.S. government export regulations, applicants must meet one of the following criteria:

(A) Qualify as a U.S. person, which includes:

U.S. citizen or national
U.S. lawful permanent resident (green card holder)
Refugee under 8 U.S.C. 1157
Asylee under 8 U.S.C. 1158

(B) Be eligible to access export‑controlled information without requiring an export authorization.

(C) Be eligible and reasonably likely to obtain the necessary export authorization from the appropriate U.S. government agency.

The company reserves the right to decline pursuing an export licensing process for legitimate business‑related reasons.

Equal Opportunity Employer Statement:

Aalyria is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. We do not discriminate based on race, color, religion, sex (including pregnancy, gender identity, and sexual orientation), national origin, age, disability status, genetic information, protected veteran status, or any other characteristic protected by law. Qualified applicants from all backgrounds are encouraged to apply.

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