Stellenbeschreibung:

Senior PLL Analog Design Engineer | Deep Tech Semiconductor Start-up | Hybrid in Aachen A deep tech semiconductor start-up redefining high-speed data communication is looking to grow its team with a Senior PLL Design Engineer in Aachen. In this senior-level position, you'll be instrumental in designing, simulating, and verifying high-performance Phase-Locked Loops (PLLs) for a variety of SoC and mixed-signal applications. You'll collaborate closely with system architects, digital designers, layout engineers, and verification teams to deliver robust, silicon-proven PLL solutions on cutting-edge process nodes like 22FDX and other FinFET/FD-SOI technologies. We're looking for someone with significant experience and leadership potential to drive our projects forward. What You'll Do:Lead the design and development of complex analog/mixed-signal PLL circuits, including VCOs, phase detectors, charge pumps, loop filters, and frequency dividers.Conduct schematic design, behavioural modeling, and transistor-level simulations using industry-standard tools like Spectre, HSPICE, and Verilog-A/AMS.Optimise PLL designs for critical performance metrics such as low jitter, low power consumption, and efficient silicon area.Partner with layout engineers to ensure design integrity and optimal performance through layout-aware design practices.Actively participate in design reviews, silicon validation, and debugging to ensure successful product realization.Generate comprehensive documentation and provide seamless support for PLL integration into larger SoC environments. What You'll Bring:M.Sc. or Ph.D. in Electrical Engineering or a related field.6+ years of hands-on experience in analog/mixed-signal IC design, with a strong emphasis on PLLs, high-speed wireline SerDes, DDR, or other high-speed applications.Deep theoretical understanding of PLL principles, jitter analysis, and noise modeling.Proven experience in designing core analog blocks such as op-amps, bandgaps, differential amplifiers, VCOs, PLLs, and DLLs.Proficiency with Cadence design tools, Spectre, and behavioral modeling languages like Verilog-A and SystemVerilog-AMS.A solid grasp of full-custom analog layout techniques, including the ability to oversee design, extraction, verification, and sign-off.Practical experience with advanced CMOS process nodes.Excellent communication skills and a collaborative mindset, thriving in a team-oriented environment. What We Offer:A highly technical and impactful role within a dynamic and fast-growing semiconductor startup.The exciting opportunity to contribute to next-generation data converter ICs and wireless communication systems.A competitive salary, attractive equity (VESOP), and comprehensive benefits package.An open, international team culture that champions innovation, ownership, and a results-driven approach.Flexibility in work location, focusing on delivering real impact. Interested? Apply directly through LinkedIn, or send your CV to [email protected] By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/about-us/privacy-notice/)

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