Formal verification engineer student

Your mission

• 10h/week, from July 2025, hybrid
• Be trained in state-of-the-art formal verification techniques
• Be part of our verification team and help us verifying customers designs
• Work on your own, with a team or lead your own project

Your profile

• Ability to work independently and in a team
• Basic knowledge in SystemVerilog/VHDL
• Business level English
• Beneficial: basic knowledge in SVA

Why us?

• Flexible working hours that allow you to be the boss of your own work
• Contribute your own ideas and manage your own development
• Remote and on-site work
• Regular team events in a young, dynamic, intercultural team
• Hands-on insight into the working world and the growth of a startup

About Us

LUBIS is a fast-growing German startup redefining how the semiconductor industry works. We tackle one of its hardest challenges — ensuring complex chips work flawlessly before they’re built.

Our mission is simple: to transform verification from a craft into a system. By structuring how teams work and automation we make chip design faster, reliable, and bug-free.

LUBIS isn’t just improving the process — we’re defining how verification is done.

#J-18808-Ljbffr