Stellenbeschreibung:

This is a unique opportunity to join a fast-moving team developing cutting-edge mixed-signal IP, including high-speed ADCs, DACs, and PLLs on advanced process nodes like 22FDX and FinFET. The role offers hands-on involvement in precision layout that directly impacts the performance and efficiency of next-generation wireless and high-speed communication systems.



Responsibilities:
• Own the physical implementation of mixed-signal circuits, including high-speed blocks such as SerDes, PLL, CDR, and LVDS.
• Collaborate closely with design engineers on custom layout, floorplanning, and physical verification to meet performance, area, and reliability goals.
• Optimize layouts for matching, low noise, minimal parasitics, and efficient area utilization across advanced process nodes.
• Perform layout verification tasks, resolving DRC, LVS, and ERC violations, and generating accurate parasitic extractions (PEX) for post-layout simulations.
• Contribute to design reviews and methodology, ensuring layout robustness across PVT variations and supporting IP integration into end products.


Requirements:
• Hands-on experience in layout of high-speed or high-resolution ADCs, DACs, and PLLs.
• Deep knowledge of layout best practices, including matching, shielding, routing, and symmetry techniques.
• Proven expertise in full-custom analog and mixed-signal IC layout.
• Skilled in using Cadence layout tools and workflows.
• Familiar with advanced CMOS technology nodes and effective in cross-functional team collaboration.



If this role is of interest please apply directly on LinkedIn or send a copy of your CV to [email protected].

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