Stellenbeschreibung:

Mixed Signal Design Engineer - Data Converters / DAC / ADC

European Tech Recruit are working closely with an exciting semicon startup, based in Aachen, who are looking for a talented Mixed Signal Design Engineer with experience in Data Converters / DAC / ADC to join their team.


In this role you will be involved in the complete development cycle - from specification and architecture to silicon validation - working at the forefront of data converter technology in advanced CMOS processes such as 22FDX and other FinFET/FD-SOI processes.


Responsibilities as Mixed Signal Design Engineer:
• Solid understanding of ADC/DAC architectures, performance metrics, design trade-offs, and criteria for deciding which ADC/DAC designs are suitable for different applications.
• Solid understanding of and experience with building block circuits for measurement sub-systems such as band-gaps, CMOS bias generators, TIAs, op-amps, filters, switched-cap circuits, LDOs, ADCs, etc.
• Extensive hands-on experience with EDA design tools such as Cadence Virtuoso, preferably with a history of successful Tapeouts.
• Develop behavioral models and perform architecture-level trade-off analysis.
• Expertise in techniques for high-precision circuit design in the presence of large device mismatch and high supply noise.
• Collaborate closely with layout engineers to ensure layout matching and parasitic-aware design.
• Experience in C / MATLAB / Verilog modeling.
• Support silicon bring-up, lab validation, and debugging of first silicon.
• Document design and verification results, and support IP integration into customer products.


Requirements:
• M.Sc. or Ph.D. in Electrical Engineering or related field.
• 10+ years of industry experience.
• Hands-on experience in mixed-signal IC design, particularly ADC/DAC circuits.
• Experience working with 16nm and below technology.
• Strong understanding of analog design fundamentals (noise, matching, linearity, stability).
• Knowledge of system-level integration and SoC interfacing.
• Proficiency with Cadence design tools, Spectre, and behavioral modeling (Verilog-A, SystemVerilog-AMS).
• Full-custom analog layout techniques and the ability to take a design and do all the layout extract verification and sign-off.
• Experience with advanced CMOS process nodes.
• Good communication skills and ability to work in a collaborative team environment.


If this role is of any interest please apply directly on LinkedIn or send a copy of your CV to [email protected].

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