Stellenbeschreibung:

Ph.D. Candidate in Functional Safety for AI Accelerators - Contract Duration 3 Years (f/m/d)

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are seeking a highly motivated PhD candidate to join the TIRAMISU project (Training and Innovation in Reliable and Efficient Chip Design for Edge AI, ).

The research will focus on the functional safety aspects of AI accelerators, aligned with ISO 26262 standards, utilizing state-of-the-art EDA tools. The PhD work involves identifying safety-critical components of AI accelerators and developing advanced safety analysis methodologies.

The goal is to develop safety mechanisms and optimize safety verification techniques, including simulation-based fault injection and formal verification, to enhance AI hardware safety. These methods will be integrated into Cadence’s functional safety toolchain, contributing to a novel methodology that improves safety verification processes and accelerates time-to-market for AI accelerators.

Required qualifications:

• MSc (or equivalent) in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline
• Solid understanding of digital IC design and verification methodologies
• Proficiency in hardware description languages (e.g., Verilog, VHDL) and programming
• Background in functional safety is desirable
• Ability to work in a hybrid model within a modern office environment

If you are interested, do not hesitate to contact us.

We’re doing work that matters. Help us solve what others can’t.

About the company

Cadence Design Systems, Inc., headquartered in San Jose, California, in the North San Jose Innovation District, is an American multinational electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Sy... (more details could be added here for completeness)

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