Senior Digital Design Verification Engineer (d/m/f) - Munich, Germany

Stellenbeschreibung:

Overview

Senior Digital Design Verification Engineer (d/m/f) – Munich, Germany. Our German client, a leading worldwide supplier of high performance optical sensors, is seeking a highly capable engineer for verification strategy and execution of digital and mixed-signal IPs.

Responsibilities

  • Define verification strategy for digital and mixed-signal IPs as per system requirements. Define testbench architecture and partition, develop verification plan, and interact with digital, mixed-signal and analog design engineers for feature extraction.
  • Apply state-of-the-art methodologies (UVM, Formal Verification) and develop efficient and reusable verification environments and testbench components. Develop IP-level and system-level testbenches maximizing coverage and reuse. Develop constrained-random tests, checkers and coverage models based on IC specifications.
  • Define infrastructure to support mixed-signal verification and analog/real-number behavioral modelling.
  • Support/perform execution of verification plans, which includes environment setup, regression running (RTL and gate-level), coverage collection, and failure debug.
  • Support technical communication with customers (and/or marketing) and other work-packages, including: presentation in design reviews, test requirements, defining/tracking/working to ensure schedule adherence and interactive problem solving.
  • Mentor junior engineers and help them develop required knowledge and experience through project work.

Qualifications

  • Master’s degree in Electrical Engineering with 7 years of experience or Bachelor’s degree with 10 years of experience with emphasis in Digital Verification or a similar specialty.
  • Expertise and technical leadership in digital verification, including testbench architecture and verification planning and execution of digital and mixed-signal designs.
  • Expertise in IPs (block-level) and integrated systems (top-level) verification with reusable components and coverage models.
  • Expertise in SystemVerilog for verification using advanced verification methodologies (UVM, SVA or similar), including constrained random and metric driven verification.
  • Experience in Formal verification.
  • Experience with EDA tools used for simulation, regressions, feature extraction and verification planning. Ability to set up and automate verification tasks is a plus.
  • Experience with System Verilog RNM and analog behavioral modelling.
  • Familiarity with digital design and analog flows and methodologies is a plus.
  • Knowledge of scripting languages (Python, Tcl, Perl) for automation and code generation.
  • Fluent in English. Excellent team player; calm professional demeanor and excellent listening skills, ability to organize and prioritize work.

Seniority level

  • Mid-Senior level

Employment type

  • Full-time

Job function

  • Engineering and Information Technology

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Stelleninformationen

  • Typ:

    Vollzeit
  • Arbeitsmodell:

    Vor Ort
  • Kategorie:

  • Erfahrung:

    2+ years
  • Arbeitsverhältnis:

    Angestellt
  • Veröffentlichungsdatum:

    04 Nov 2025
  • Standort:

    München

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