We are looking for an experienced Senior or Principal Verification Engineer to join our clients’ innovative team.
This is a remote role based in Germany, offering you the flexibility to work from any location in Germany while being part of a global, inclusive, and diverse team. As a permanent full-time employee, you will be responsible for all aspects of verification planning, management and implementation.
You will be directly involved with helping build and grow client relationships.
Qualifications
7 years of project-proven verification experience
Experienced SystemVerilog/UVM developer
Specification level checks for several different protocols, e.g. AXI, DDRx, PCIe, USB
Verification planning
Ownership of work, from planning to implementation
Experience dealing directly with strict deadlines and technical challenges
Nice To Have
Specman/e expertise to a similar level
C/C++ developing, or integrating, reference models into SystemVerilog/UVM environments