ASIC Verification Engineer 4 - SOC Subsystem Integration

They gather information about your interactions on the site, such as which pages you visit frequently, how long you stay, and the links or buttons you click. They help us record any difficulties you have with the website and help us to evaluate the effectiveness of our advertising. By analyzing this data, we can understand what aspects of our site are effective and identify areas for improvement.* This is a secondary processing purpose.* This is a secondary processing purpose.* This is a primary processing purpose.* This is a secondary processing purpose.ASIC Verification Engineer 4 - SOC Subsystem Integration page is loaded## ASIC Verification Engineer 4 - SOC Subsystem Integrationlocations: Germany- Braunschweigtime type: Full timeposted on: Publié aujourd'huijob requisition id: R As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.**How You Will Contribute:**The Wavelogic family of products is widely used in Ciena's optical fiber transmission solutions and is one of the main contributors to Ciena's success in the telecommunications industry. To further strengthen our team, we are looking for a hardworking digital verification engineer who will be involved in the verification of these products, working within a team of digital design engineers, verification engineers and architects. Your role as a digital verification engineer will be required to propose and implement innovative verification strategies, in order to thoroughly simulate and validate functional blocks and subsystems for the Wavelogic family of products.* As lead digital verification engineer you are required to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects.* You will produce verification plans for blocks and IP toplevel and lead reviews with the team, architects and firmware engineers if applicable* You are held responsible for the complete and detailed validation of one or more architectural functional blocks or the IP toplevel by using an appropriate combination of simulation, formal and coverage methods.* You will lead the verification planning, functional coverage definition and possibly formal verification test plans.* You are accountable for the creation or integration of the test bench environment(s) and/or components, agents, scoreboard, and all test scenarios related to your architectural functional block or the IP toplevel using System Verilog UVM and/or C where applicable.* You will perform coverage-driven verification, monitor regressions and debug resulting failures with the help of the function's designer.* Lead the verification of a chiplevel IP* Collect the verification status and reporting on a regular basis* Improve the existing verification methodology by integration of tools and creation of new innovative ideas* Lead team or supervise interns where appropriate**The Must Haves:*** Expert-level experience (10+ years) with functional verification of complex digital circuits* Electrical or computer engineering, computer science or other applicable completed scientific degree at the BEng/BSc, MEng/MSc or higher level* Expert-level programming skills using System Verilog, C/C++, UVM, SVA, as well as experience with verification tools from major EDA vendors.* A highly motivated self-starter, able to work independently, while being a great teammate* Ability to methodically solve complex technical problems* Excellent organization, written and oral (English) communication skills**Assets:*** Experience with formal verification methods and tools* Experience with verification of DSPs for optical communication systems* Experience with using GIT for source code management and revision tracking* Experience with using Jira for schedule planning, assignment tracking and bug reporting* Experience with programming languages such as Python, Matlab, Make, bashJoin our to get relevant job alerts straight to your inbox. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.Ciena is an Equal Opportunity Employer, including disability and protected veteran status.If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.
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