Senior Silicon Physical Design Engineer

Senior Silicon Physical Design Engineer – Axelera AI

Axelera AI is not your regular deep‑tech startup. We are creating the next‑generation AI platform to support anyone who wants to help advancing humanity and improve the world around us. In four years, we raised $120 million, built a world‑class team of 220+ employees (including 49+ PhDs with more than 40,000 citations), spanning 17 countries and offices in Belgium, France, Switzerland, Italy, the UK, and headquartered at the High Tech Campus in Eindhoven, Netherlands. We have launched our Metis™ AI Platform, achieving a 3‑5x increase in efficiency and performance, and have a strong business pipeline exceeding $100 million.

Position Overview

As a Senior Silicon Physical Design Engineer at Axelera AI, you will play a crucial role in developing cutting‑edge multi‑core in‑memory compute SoCs. Leveraging your expertise in ASIC Physical Design from RTL to GDS, you will be responsible for all aspects— synthesis, floorplanning, place‑and‑route, extraction, timing analysis, physical verification, EMIR sign‑off, and formal verification— and will collaborate closely with architecture and RTL teams to ensure successful project execution.

Key Responsibilities

• Perform synthesis, floorplanning, place‑and‑route, extraction, timing analysis, and physical verification.
• Generate constraints, conduct timing analysis, and optimize design.
• Execute clock tree synthesis (CTS) and custom clock‑building techniques.
• Integrate IPs, including memories, I/Os, embedded processors, DDR, networking fabrics, and analog IPs.
• Use EDA tools such as Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, and Calibre.
• Develop automation scripts in Python, Tcl, Bash, and contribute to flow development.
• Debug and solve technical challenges related to physical design.
• Collaborate with architecture, RTL, and verification teams.

Qualifications

• 10+ years of experience in Physical Design (RTL to GDS).
• Strong communication and teamwork skills.
• Expertise in all aspects of physical design.
• Hands‑on experience with leading EDA tools (Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Redhawk, and Calibre).
• Proficiency in clocking techniques and CTS.
• Experience in IP integration across various domains.
• Strong scripting skills (Python and Tcl).
• Proven problem‑solving and debugging capabilities.
• Fluent in English (spoken and written).

Highly Preferred

• Experience in floorplanning and top‑level integration.
• Knowledge of chip‑package‑board co‑simulation and packaging.
• Experience working with EDA vendors to resolve tool issues.
• Understanding of semiconductor device physics and multi‑domain design.

Location

• Work from one of our Axelera AI offices (Leuven in Belgium, Amsterdam and Eindhoven in the Netherlands, Florence and Milan in Italy or Bristol in the United Kingdom) if you are already based in the vicinity.
• Work fully remotely from any European country (incl. the UK) you are already in.
• Relocate with us and work from Italy (Florence or Milan) or the Netherlands (Amsterdam or Eindhoven).
• Priority will be given to candidates based in Belgium or Italy.

What We Offer

Compensation includes a pension plan, extensive employee insurances, and an option to receive company shares. You will join a dynamic, fast‑growing, international organization with an open culture that supports creativity and continual innovation. Collaborative ownership and freedom with responsibility are characteristic of the way we act and work as a team.

Equal Opportunity Statement

At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI.

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