Staff / Principal Functional Verification Engineer (m/f/d)

Staff / Principal Functional Verification Engineer (m/f/d)

Location: Mannheim, Germany (Hybrid) or Villach, Austria (Hybrid)
Employment Type: Permanent, Full-Time

Salary: Competitive and negotiable

Role Overview

We are looking for an experienced Staff / Principal Functional Verification Engineer to join our team delivering high-performance on-chip network (NoC) solutions. You will develop and maintain UVM SystemVerilog verification environments, collaborate with design teams, and ensure high-quality, on-time product releases.

Responsibilities

• Develop and maintain UVM SystemVerilog verification environments for NoC IP
• Define and execute functional verification plans
• Design and enhance verification testbenches
• Debug complex design and verification issues
• Drive coverage closure and monitor regression runs
• Collaborate with design and cross-functional teams for successful product releases

Requirements

• B.S./M.S. in Electrical Engineering, Computer Engineering, Physics , or related field
• 10+ years of relevant experience
• Strong expertise in UVM SystemVerilog and SystemVerilog Assertions
• Experience with Cadence Xcelium/vManager preferred
• HDL coding experience (Verilog/SystemVerilog/VHDL) a plus
• Scripting skills: Python, TCL, Bash
• Excellent English communication skills ; German a plus

What We Offer

• Flexible working hours and hybrid/remote options
• Competitive salary and career growth opportunities
• Team-oriented, supportive environment with regular events
• Workation option: up to six weeks per year

Locations: Mannheim, Germany or Villach, Austria

If you are interested, please get in touch and send your CV to