System on Chip (SoC) Verification Engineer (all genders)

System on Chip (SoC) Verification Engineer (all genders)

Join to apply for the System on Chip (SoC) Verification Engineer (all genders) role at Fraunhofer IIS.

The Fraunhofer‑Gesellschaft currently operates 75 institutes and research institutions throughout Germany and is the world’s leading applied research organization. Around 32,000 employees work with an annual research budget of 3.4 billion euros. The Fraunhofer Institute for Integrated Circuits IIS, located in Erlangen, is the largest institute of the Fraunhofer‑Gesellschaft with more than 1,200 employees.

Welcome to the Fraunhofer Institute for Integrated Circuits IIS, headquartered in Erlangen! As the largest institute within the Fraunhofer‑Gesellschaft, we have been conducting research for over 30 years in diverse fields such as artificial intelligence, microelectronics, sensor systems, data acquisition, signal processing, and signal transmission. Talented individuals from various engineering and natural science disciplines will find a wide range of exciting research topics under one roof. Highlights include neuromorphic computing, 5G/6G mobile communication technologies, generative AI in speech and signal processing, and X‑ray imaging for e‑mobility.

We bring chip design back to Europe!

For a more technologically independent Europe, we aim to develop Fraunhofer IIS into a European IC Design Center for trusted and energy‑efficient high‑speed ICs by 2026. As a leading competence center for digital chip design, we deliver essential cutting‑edge technologies in the areas of exascale high‑performance computing and trusted electronics. In addition, we offer sophisticated digital design services based on RISC‑V. Our target customers are design houses, semiconductor manufacturers, SMEs, and system integrators.

Responsibilities

• Understand the nuances of RISC‑V architectures and industry‑standard low‑power architectures to build block/chip level testbenches using best‑in‑class verification methodologies.
• Translate design specifications into comprehensive verification plans in collaboration with system architects.
• Develop and maintain reusable testbenches for IP/block‑level verification and support IP integration verification.
• Create smart, constraint‑random and directed test cases tailored to RISC‑V SoCs.
• Build and analyze coverage models, and refine tests to close coverage gaps.
• Debug test failures, manage bug tracking, and ensure coverage closure.
• Lead verification reviews to uphold coding quality and best practices in SoC verification.
• Prepare, run, and evaluate regression runs.

What You Bring To The Table

• University degree in electrical engineering, IT/computer science or a related field.
• Solid understanding of digital logic design and RISC‑V‑based SoC architecture.
• Proven experience with SystemVerilog and UVM‑based verification environments.
• Very good English and good German language skills.
• Proactive and independent mindset.

Nice to Have

• Familiarity with C/C++, assembly and object‑oriented languages such as Python.
• Knowledge of industry‑standard interfaces and bus protocols (e.g., AXI).
• Experience with IP verification methods, integration verification specific to RISC‑V and embedded CPU verification.
• Interest in low‑power verification techniques and formal verification tools (e.g., JasperGold).

What You Can Expect

• Our institute culture: A friendly and supportive working atmosphere within an international team.
• Exciting activities: Work with customers and partners worldwide, offering a highly innovative environment.
• Room for creativity: Generous creative freedom to develop and implement ideas.
• Personal development: Top‑of‑the‑line equipment and regular training.
• Flexible working hours: Balance between private and professional life.
• Equal opportunity: Career program “Fraunhofer TALENTA”.

More information about our employer offers on our website: Fraunhofer IIS Jobs

The position is initially limited to 2 years with the aim to extend it subsequently. The weekly working time is 39 hours. The position can also be filled on a part‑time basis with a preference, however, to have it filled as close to a full‑time position as possible.

We value and promote the diversity of our employees’ skills and therefore welcome all applications – regardless of age, gender, nationality, ethnic and social origin, religion, ideology, disability, sexual orientation and identity.

Appointment, remuneration and social security benefits based on the public‑sector collective wage agreement (TVöD).

Ready for a change? Apply now and make a difference! Please submit: cover letter, CV, and grade sheets.

Do you have questions about the application process? Our recruiter Nina Wörlein is here for you: Phone +49 9131 776‑1678.

Fraunhofer Institute for Integrated Circuits IIS

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