ASIC Physical Design, Staff Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self‑driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high‑performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a driven and innovative engineer passionate about pushing the boundaries of semiconductor technology. With at least 5+ years of post‑graduate experience in ASIC physical design, you possess a comprehensive understanding of advanced IP implementation, especially in DDR, HBM, or HBI protocols. Your expertise in utilizing industry‑standard EDA tools like Design Compiler (DC), IC Compiler II (ICC2), PrimeTime‑SI, and Formality Check (FC) sets you apart. You are adept at achieving timing closure at frequencies above 2GHz, and you thrive on solving complex integration challenges, such as mixed‑signal hard macro IP integration and building efficient clock trees with precise skew balancing.

Collaboration is at your core – you communicate clearly and effectively with both local and US‑based colleagues, regularly engaging in technical discussions and knowledge sharing. You are a natural leader, frequently guiding junior team members and contributing to project leadership roles. Your ability to independently resolve issues using creative approaches ensures project success, while your adaptability allows you to navigate the fast‑paced and ever‑evolving landscape of physical design. You are eager to learn, open to exploring new technologies, and maintain a growth mindset, continually seeking out opportunities to refine your skills and expand your expertise. Above all, you are committed to delivering world‑class IP solutions that empower the next generation of high‑performance silicon chips.

What You’ll Be Doing:

• Implement and integrate cutting‑edge DDR, HBM, and HBI IPs at advanced technology nodes, ensuring optimum performance and reliability.
• Drive timing closure for high‑speed designs operating above 2GHz, employing advanced techniques and methodologies.
• Collaborate daily with local and US‑based teams to align on project goals, technical challenges, and best practices.
• Lead the development of efficient clock tree structures, achieving tight skew balancing for robust design integration.
• Resolve complex design and integration issues independently, utilizing creative problem‑solving and technical acumen.
• Guide and mentor junior engineers, sharing knowledge and fostering a culture of continuous learning and innovation.
• Provide regular project status updates to management and represent the organization in cross‑functional business unit initiatives.

The Impact You Will Have:

• Deliver world‑class DDR/HBM/HBI IP solutions that enable Synopsys customers to build leading‑edge silicon products.
• Enhance the reliability and performance of high‑speed memory interfaces in next‑generation chip designs.
• Champion best practices in physical design, driving process improvements and technical excellence within the team.
• Support Synopsys’ leadership in the semiconductor industry by contributing to innovative solutions and IP advancements.
• Strengthen collaboration across global teams, ensuring seamless integration and knowledge transfer.
• Mentor and develop future leaders in physical design, multiplying the team’s long‑term impact.

What You’ll Need:

• Minimum 5+ years’ post‑graduate experience in ASIC physical design or related engineering roles.
• Proficiency with EDA tools such as DC, ICC2, PT‑SI, and FC.
• Hands‑on expertise in DDR/HBM/HBI timing closure, IP implementation, and integration.
• Strong understanding of clock tree synthesis, skew balancing, and mixed‑signal hard macro IP integration.
• Ability to independently resolve complex technical challenges and provide project leadership.

Who You Are:

• Excellent communicator who thrives in collaborative, multicultural environments.
• Analytical thinker with a passion for problem‑solving and innovation.
• Adaptable and eager to learn new technologies and methodologies.
• Natural leader who enjoys mentoring and guiding junior team members.
• Proactive, self‑motivated, and able to manage multiple priorities effectively.

The Team You’ll Be A Part Of:

You will join the Synopsys DDR/HBM/HBI IP implementation team, a dynamic group of talented engineers focused on delivering state‑of‑the‑art memory interface solutions. The team is known for its collaborative spirit, technical excellence, and commitment to innovation. Together, you’ll tackle challenging design and integration problems, support each other’s growth, and contribute to the success of Synopsys’ industry‑leading IP portfolio.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.