Junior Engineer for Electrical Parametric Test Structures

Company

GlobalFoundries® Inc. (GF®) is one of the world's leading semiconductor manufacturers. GF redefines innovation and semiconductor manufacturing by developing and delivering feature‑rich process technology solutions with leading performance in all growth markets. GF offers a unique mix of design, development and manufacturing services. With a talented and diverse team and manufacturing locations in the U.S., Europe and Asia, GF is a trusted technology provider to its global customers. GF employs approximately 13,000 people, including more than 3,000 in Dresden, Germany.

Role Overview

We are looking for an encouraged and motivated Junior Engineer to support our development activities in the Integration, Product Life Cycle Management (PLCM) Department in Dresden, Germany. You will be a member of a highly skilled team working on development, implementation, debugging and optimization of existing test structures and procedures. The team manages the electrical test structures implementation for technology development, new product introduction (NPI) projects, and volume production monitoring in leading‑edge CMOS technologies.

Your Job

• Ensuring the correct measurement structure sets have been placed on particular NPIs, Multi Program Wafer (MPW) projects or technology development test chips.
• Definition and debugging of parametric measurement programs for NPIs, MPWs or technology development test chips.
• Development of electrical test structures in collaboration with Process Integration Front‑End of Line (FEoL), Middle‑of‑Line (MoL), Back‑End of Line (BEoL), Device development and Yield Engineering teams.
• Continuous improvement of measurability aspects and detection limits of existing electrical test structures in agreement with production and customer needs, with potential to invent novel measurement concepts.
• Validation of test structures and measurement programs with test floor and lab measurements.
• Analyzing electrical characteristics and behavior of test structures throughout the entire portfolio of active and passive devices, including gap identification when comparing silicon results with Spice model expectations and design manual targets.
• Execution of test structure layout design and verification with industry standard tools (Cadence Virtuoso, Mentor Graphics Calibre).

Required Qualifications

• Degree in Electronics Engineering, Physics or Communication Engineering with passion for next‑generation semiconductor technologies.
• Knowledge of transistor physics and CMOS fabrication process enabling deep understanding of interactions between electrical behavior, design layout and manufacturing process.
• Team player with strong communication skills, able to efficiently exchange ideas and share results within and between teams with different technical backgrounds.
• Competence in written and spoken English and solid knowledge in use of standard office software (Excel/PowerPoint).

Preferred Qualifications

• Experience in statistics and data analysis or layout with Cadence Virtuoso and/or Mentor Graphics Calibre or compact modeling of semiconductor devices.

Compensation and Benefits

The position is open‑ended and will be filled as soon as possible.

• 13th month salary, bonus payments, assistance with relocation to Dresden.
• Family friendly part‑time models, trust flextime, salary conversion into free time.
• Career stages for every job, internal qualification offers, promotion of external educational qualifications.
• On‑site gym, beach volleyball court, bike leasing, subsidised employee restaurant.
• Cooperation at eye level – everyone is on first name terms with us, budget for individual team events, social commitment via GlobalGives.

Diversity is part of our corporate DNA. We encourage women to apply and welcome applications from people with disabilities.

The job advertisement refers to a position up to ENG/IC1 GlobalFoundries ETV.

Information about our benefits can be found at