Physical Design Engineer

ROLE:

Physical Design Engineer – (RTL2GDS2) – Chiplet / High-Speed Interface IP LOCATION:

Mannheim, Germany OR Villach, Austria SALARY:

Negotiable DURATION:

Permanent

Responsibilities: Support and execute the full RTL-to-GDS2 implementation flow Perform physical design and sign-off verification for high-performance interface IP (SerDes / UCIe) and associated test chips Port IP to new technology nodes and metal stacks, identifying and resolving implementation challenges Optimize designs for timing, power, and area (PPA) Evaluate and implement enhancements using the latest EDA tool capabilities Contribute to continuous improvement of internal physical design methodologies and development flows Collaborate closely with the analog design team to ensure seamless mixed-signal integration

Requirements: 2+ years of professional experience in physical implementation Hands-on experience with EDA tools from major vendors (place & route, timing, physical verification) Fundamental knowledge of RTL design (Verilog or SystemVerilog) Understanding of modern CMOS process technologies Scripting experience in TCL