Senior Design Verification Engineer

A thriving and fast growing start up in the South West of Germany is looking for a Senior Functional Verification Engineer. You will be contributing to the NoC solutions and work closely together with the digital design team and cross‑functional groups to support a successful and on‑time product release.

Your responsibilities will include the following:

• Develop and maintain UVM SystemVerilog verification environments for our NoC IP.
• Elaborate and work on IP and product specification documents.
• Create and execute comprehensive functional verification plans.
• Design, implement and continuously improve verification test benches.
• Understand and debug identified errors.
• Work on coverage closure and monitor the daily regression runs.

Your qualifications and skills:

• B.S./M.S. degree in Electrical Engineering or similar.
• Minimum 5 years of work experience in Functional Verification.
• Good knowledge of UVM SystemVerilog and SystemVerilog Assertions.
• Cadence XCELIUM and vManager is a plus.
• HDL is a plus.
• Python, TCL and Bash.
• Good written and oral communication skills in English are required.

Seniority level

Mid‑Senior level

Employment type

Full‑time

Job function

Staffing and Recruiting