Senior Digital Design Verification Engineer (d/m/f) - Munich, Germany

Senior Digital Design Verification Engineer (d/m/f) - Munich, Germany at Albelissa Engineering, IT & Digital Solutions

Responsibilities

• Define verification strategy for digital and mixed-signal IPs as per system requirements; design testbench architecture and partition, develop verification plans, and interact with digital, mixed-signal, and analog design engineers for feature extraction.
• Apply state‑of‑the‑art methodologies (UVM, Formal Verification) to develop efficient and reusable verification environments and testbench components, creating IP‑level and system‑level testbenches that maximize coverage and reuse.
• Develop constraint‑random tests, checkers, and coverage models based on IC specifications.
• Define infrastructure to support mixed‑signal verification and analog/real‑number behavioral modelling.
• Execute verification plans, including environment setup, regression running (RTL and gate‑level), coverage collection, and failure debugging.
• Communicate technically with customers (and/or marketing) and other work‑packages; present at design reviews, define and track test requirements, ensure schedule adherence, and solve problems interactively.
• Mentor junior or younger engineers, guiding them to acquire necessary knowledge and experience through project work.

Education & Experience

• Master’s degree in Electrical Engineering with 7 years of experience, or Bachelor’s degree with 10 years of experience, with an emphasis in Digital Verification or a similar specialty.
• Expertise and technical leadership in digital verification, including testbench architecture and verification planning and execution for digital and mixed‑signal designs.
• Proficiency in IP (block‑level) and integrated system (top‑level) verification using reusable components and coverage models.
• Strong background in SystemVerilog for verification using advanced methodologies (UVM, SVA or similar), including constrained random and metrics‑driven verification.
• Experience in formal verification.
• Familiarity with EDA tools for simulation, regressions, feature extraction and verification planning; ability to set up and automate verification tasks is a plus.
• Experience with SystemVerilog RNM and analog behavioural modelling.
• Knowledge of scripting languages (Python, Tcl, Perl) for automation and code generation.
• Fluent in English.
• Excellent team player with a calm professional demeanor, strong listening skills, and the ability to organize and prioritize work.

Required Skills Summary

• University degree in Electrical Engineering with 7+ years (or Bachelor with 10+ years) of experience; emphasis on Digital Verification.
• Expertise in testbench architecture, verification planning, and execution for digital and mixed‑signal designs.
• Experience with IP and integrated system verification, SystemVerilog (UVM, SVA), constrained random and metrics‑driven methods.
• Formal verification experience.
• EDA tool proficiency; SystemVerilog RNM and analog modelling experience.
• Python, Tcl, Perl scripting skills.
• English fluency.
• EU citizenship / German work permit holder.

Seniority Level

• Mid‑Senior level

Employment Type

• Full‑time

Job Function

• Engineering and Information Technology

Additional Information

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