ASIC Verification Engineer

A leading global technology organisation within the semiconductor sector is expanding its ASIC engineering capability. We are seeking an experienced ASIC Verification Engineer to take a central role in verifying complex mixed-signal and digital ASIC platforms.

This position offers the opportunity to work on advanced silicon designs within a highly skilled, international engineering environment.

Key Responsibilities

• Define and execute advanced verification strategies for complex ASIC developments
• Develop, maintain, and enhance UVM-based verification environments
• Perform formal verification and directed testing to ensure design integrity and robustness
• Collaborate closely with design, system, and architecture teams across the full ASIC lifecycle
• Drive coverage closure and debug issues at RTL and gate-level abstraction
• Contribute to the ongoing improvement of verification methodologies, flows, and best practices

Must-Have Experience

• Deep expertise in ASIC verification methodologies including UVM, formal verification, and directed testing
• Strong hands-on experience using Specman e as a verification language
• Solid understanding of the ASIC design process and digital design methodologies
• Proven track record verifying ASICs using advanced verification and simulation toolchains
• Good working knowledge of design abstractions including RTL, gate-level, and SystemC

Nice to Have

• Basic understanding of object-oriented software design principles
• Experience with scripting languages such as Python
• Knowledge of power-aware simulation methodologies (e.g. UPF)
• Familiarity with functional safety concepts and standards

Why Apply

• Work on technically complex and challenging ASIC developments
• Join a highly capable, innovation-driven engineering culture
• Long-term career development within a global semiconductor organisation

For a confidential discussion or to learn more, please get in touch directly.