CAD Logic Equivalence Checking (LEQ) Engineer - m/f/d

CAD Logic Equivalence Checking (LEQ) Engineer - m/f/d

We are seeking a CAD LEQ (Logical Equivalence Checking) Engineer to develop, deploy, and support equivalence checking methodologies across complex SoC programs. This role focuses on ensuring functional correctness between RTL, synthesized netlists, and post‑implementation designs, while driving scalable, robust sign‑off flows.

Responsibilities

• Own and maintain LEQ sign‑off methodology across RTL-to‑GDS flows
• Develop and support flows using tools such as Cadence Conformal and equivalent industry solutions
• Drive power‑aware equivalence checking including CPX flows
• Enable ECO flows, ensuring safe and correct implementation of late‑stage design changes
• Debug equivalence failures and perform root‑cause analysis across RTL, synthesis, and PnR stages
• Collaborate with design, synthesis, PD, and power teams to resolve mismatches and improve convergence
• Optimize runtime, capacity, and scalability of LEQ flows for large SoCs
• Define best practices, guidelines, and automation for LEQ usage across projects
• Partner with EDA vendors to resolve tool issues and drive feature improvements

Minimum Qualifications

• BSc/MSc in Electrical Engineering or Computer Science
• 5+ years of experience in VLSI industry
• Strong understanding of: RTL design, Synthesis and netlist transformations, low‑power design (UPF concepts)
• Hands‑on experience with LEQ tools (Cadence Conformal, Synopsys Formality)
• Strong debugging and scripting skills (TCL, Python)

Preferred Qualifications

• Experience with power‑aware LEQ and low‑power verification flows
• Familiarity with synthesis and PnR flows
• Experience in large‑scale SoC environments and multi‑site collaboration
• Exposure to ECO flows and late‑stage sign‑off methodologies
• Experience working with EDA vendors and driving tool improvements

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