Design Verification Engineer

Location: Dresden, Germany (Hybrid)

Contract: Freelance / Contractor

Duration: 6-12 Months+

Overview

We are seeking an experienced Verification Engineer to support the development of advanced sensor and semiconductor products within a leading R&D environment. You will be responsible for verifying complex digital IP and SoC designs, working closely with design teams to ensure robust and high-quality silicon delivery.

Responsibilities

• Develop and maintain verification environments using Specman e .
• Create test plans, test cases, checkers, monitors, and scoreboards.
• Execute constrained-random and coverage-driven verification.
• Perform functional coverage analysis and drive coverage closure.
• Debug simulation failures and identify root causes.
• Collaborate with RTL designers to resolve design and verification issues.
• Support regression testing and verification sign-off activities.

Required Skills

• Proven expertise with Specman e .
• Experience with constrained-random verification methodologies.
• Strong understanding of digital design and verification flows.
• Experience with Cadence simulation and debugging tools.
• Ability to create verification environments from specification through to sign-off.
• Strong debugging and problem-solving skills.
• SystemVerilog and UVM.
• Mixed-signal, MEMS, or sensor-based products.