Design Verification Engineer

In this role you verify RISC-V processors and extensions and drive the verification strategy for a fast-growing cyber-resilient semiconductor platform. You will collaborate with an international team to deliver verification activities from plan to finish, using automated flows to improve quality and efficiency. You will own design blocks, run simulations, and perform root-cause analysis to resolve complex issues. The position sits at Codasip’s Munich design center, contributing to cutting-edge CHERI-enabled RISC-V architectures and next‑gen CPU verification.

• Verify RISC-V processors and extensions
• Develop verification solutions including test benches and stimulus generation
• Collaborate with engineers to deliver verification across a component or subsystem
• Define verification strategies for blocks and subsystems
• Review specifications from a verification perspective
• Run simulations, hunt bugs, and perform root-cause analysis
• Define, estimate, prioritise and track work
• Track and report verification metrics and craft automated verification flows

• Commercial experience with functional processor verification methodologies (simulators, test generation, coverage, gate-level simulation)
• Knowledge of verifying CPU architectures or other IP
• Fluency in SystemVerilog, Python, C++, Rust, etc.
• Ownership of a design block in verification
• Linux proficiency for automation
• Versioning tools familiarity (Git, SVN)
• Knowledge of RISC-V Architecture
• Strong analytical thinking and teamwork
• Ability to collaborate across teams to debug and find root causes

• analytical thinking
• team collaboration
• cross-team communication
• SystemVerilog
• Python
• C++