Device Design Engineer — SiC Power Devices (Multiple Levels)

Seniority: Mid / Senior / Lead / Principal

About the Role:

At L&T Semiconductor Technologies (LTSCT), we are building a world-class WBG organization and looking for Device Design Engineers across multiple seniority levels (Mid-level to Lead/Principal) to drive the end-to-end development of next-generation Silicon Carbide (SiC) power devices, with potential future expansion into GaN and UWBG technologies.

In this role, you will take ownership of the core SiC device lifecycle—from concept, TCAD modeling, and layout to DOE definition, process integration, data analysis, and support for characterization and reliability.

Key Responsibilities:

• Device Design and Layout: Define and optimize SiC power device structures (MOSFETs, Diodes, JFETs with attention to emerging architectures such as Super Junction and FinFET-type designs), across voltage nodes, structuring device DOEs and translating designs into mask‑ready layouts (GDSII) through tape‑out.
• TCAD Simulations: Perform calibrated TCAD device and process simulations to model physical behavior, validate device architectures, and benchmark performance metrics across voltage nodes.
• Foundry Interface & Lot Management: Interface directly with external foundries to define, plan, launch, negotiate, and track wafer lots, while acting as the technical counterpart across the overall process flow and on key process steps to ensure execution aligns with device targets.
• Data Analysis & Characterization: Analyze parametric, PCM, and wafer‑level data to extract physical insights, iterate device designs, and benchmark key figures‑of‑merit (FOMs).
• Reliability & Testing Support: Support testing and reliability teams with device characterization (static/dynamic), stress evaluation (e.g., short‑circuit, UIS, HTGB/HTRB), and failure analysis for automotive/industrial standards.
• IP & Technical Dissemination (Senior/Lead/Principal levels): Drive patent generation, author technical publications, and represent the team at industry conferences and technical forums.
• Stakeholder & Project Coordination (Senior/Lead/Principal levels): Provide technical mentorship, support project‑level tracking, and manage relationships with customers, research partners, foundries, and cross‑functional internal teams.

Requirements

• Education: Master's degree or PhD in Electrical Engineering, Microelectronics, Physics, or a related field.
• SiC Expertise: 6+ years of hands‑on experience in SiC power semiconductor device physics and design (experience with GaN or other WBG/UWBG materials is highly valued).
• TCAD & Layout: Proven experience with TCAD simulation tools and mask layout design (GDSII).
• Process Awareness: Working knowledge of SiC‑specific process steps (epitaxy, gate oxide formation, ohmic contact formation, implant/anneal activation) sufficient to engage critically with foundry process teams.
• Data Analysis: Strong skills in wafer data analysis (e.g., JMP, Python) and parametric characterization.
• Reliability Awareness: Familiarity with device testing, failure analysis workflows, and automotive/industrial standards (AEC-Q101, JEDEC).
• Track Record: Documented technical background supported by patents, peer‑reviewed publications, or industry conference contributions.
• Soft Skills & Interpersonal Communication: Excellent interpersonal and collaborative skills, strong team‑oriented mindset, problem‑solving attitude, and the ability to articulate complex technical concepts to both internal stakeholders and external partners/customers.