Electronic-Photonics IC Mask Data Preparation & GDS Data Integration Engineer (f/m/d)

In this role you own the complete tape-out flow for a graphene photonics platform, ensuring seamless data integration from GDS to mask release. You will align design, fabrication, testing, and packaging requirements across multiple nodes, driving DFX coordination across functionality, manufacturing, testing, and reliability. You work closely with mask shops, foundries, EDA vendors, and cross‑functional teams to meet fab specifications and deliver first‑silicon reliability. This opportunity lets you shape advanced photonics/tape-out processes on a 300 mm platform, contributing to high‑impact, energy‑efficient computing networks.

• comprehensive benefits package
• outstanding insurance
• pension
• virtual stock options

• Own mask GDS/MDP integration and the complete tape-out flow, including verification and final mask sign-off
• Lead GDS and reticle-to-fab delivery, formal mask release activities, and ensure compliance with fab specifications
• Drive DFM and DFT integration with yield optimization, hotspot mitigation, layout optimization, and implementation of scan chains, test pads, and optical probe structures within GDS
• Design and integrate special GDS structures (kerf, seal ring, frame, scanner marks, metrology & PCM structures, ESD layouts, RDL interfaces)
• Act as primary interface between mask shops, lithography/metrology teams, EDA vendors, and cross-functional teams across regions
• Maintain GDS version control and audit trails while supporting first-silicon debug and layout-based failure analysis

• MS or PhD in Electrical Engineering, Physics, or related field with 5+ years in semiconductor or photonics tape-out, layout integration, and MDP
• Strong expertise in GDSII/OASIS, DRC/LVS/ERC, and tools like Calibre and Synopsys ICV (MDP job deck authoring and JDV)
• Hands-on experience with production tape-out flows including DFM, DFT, ESD, seal ring/kerf, and RDL layout
• Familiarity with OPC flows for advanced photonics or CMOS nodes and coordination with mask shops and foundries
• Experience with Photonic IC technologies (Si, SiN) or 2D-material integration, RF photonics, or photonic/electronic co-design EDA tools such as Cadence EPIC or Lumerical
• Background with mask shops or EDA software environments (e.g., Synopsys, Siemens, Cadence, Toppan, Photronics, Compugraphics, Tekscend) is highly desirable

• Cross-functional collaboration
• Strong communication with external partners
• Attention to detail
• GDSII/OASIS
• DRC/LVS/ERC verification
• MDP/JDV tooling