Field-Programmable Gate Arrays Engineer

Freelance FPGA Engineer – Radar Signal Processing

Location: Munich, Germany (hybrid / on‑site presence required)

Contract Type: Freelance / Contract

Start Date: ASAP

Project Overview

A leading Munich‑based technology organisation is seeking an experienced Freelance FPGA Engineer to support the development of advanced radar signal processing systems .

You will join an established hardware and signal‑processing team working on high‑performance radar platforms used in safety‑critical and mission‑critical environments. The project focuses on real‑time data processing , low‑latency DSP pipelines , and high‑speed sensor interfaces , implemented on modern FPGA architectures.

Key Responsibilities

• Design, implement, and optimise FPGA‑based radar signal processing pipelines
• Develop and maintain VHDL / SystemVerilog RTL for real‑time DSP applications
• Implement signal processing blocks such as:
• FFTs and filtering chains
• Data aggregation and reduction
• Interface FPGAs with high‑speed ADC/DACs , RF front‑ends, and external processors
• Perform simulation, verification, and debugging at RTL and system level
• Collaborate closely with algorithm, RF, and system engineers
• Support hardware bring‑up, integration, and laboratory testing
• Produce clear technical documentation aligned with regulated environments

Required Skills & Experience

Technical

• Strong professional experience in FPGA development (5+ years recommended)
• Excellent knowledge of VHDL and/or SystemVerilog
• Proven experience with radar or high‑throughput DSP systems
• Solid understanding of:
• Fixed‑point arithmetic
• Pipelined architectures
• Hands‑on experience with vendor toolchains (e.g. Xilinx Vivado , Intel Quartus )
• Experience with simulation and verification tools (ModelSim, Questa, Riviera, etc.)
• Familiarity with high‑speed interfaces (LVDS, JESD204, Ethernet, PCIe – depending on platform)
• Experience in aerospace, defence, or regulated industries
• Knowledge of software‑defined radio (SDR) concepts
• Exposure to safety‑critical or high‑reliability systems
• Experience with hardware bring‑up and lab‑based debugging (logic analysers, scopes)