Front-End & Back-End SoC Engineering, Principal Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You are a SoC Technical Lead Engineer with 15+ years of experience and a strong record of delivering complex SoC and ASIC products from architecture definition through tapeout. You combine deep front-end and back-end design expertise with proven leadership skills to guide cross-functional engineering teams and deliver high-quality silicon on schedule. You bring hands‑on experience in SoC design and implementation, with the ability to anticipate the downstream impact of early planning and effort‑estimation decisions.

What You’ll Be Doing

• Technically Lead end-to-end SoC and ASIC development from architecture definition through GDS tapeout, owning technical strategy, implementation methodology, and delivery execution
• Define and drive front-end activities including SoC architecture, IP subsystem integration and hardening (PCIe, DDR, UCIe, Ethernet), RTL development, functional verification planning, and DFT implementation with scan insertion and ATPG
• Own back-end physical implementation including floorplanning, hierarchical partitioning, place and route, clock tree synthesis, PPA optimization, and timing closure using Synopsys Fusion Compiler, Primetime, PrimeClosure
• Drive specification-driven constraints development for functional and DFT modes, manage STA, IR-drop, EM analysis, DRC/LVS signoff, formal verification, and ECO strategies using PrimeTime, PrimePower, Redhawk SC, and Formality
• Work with geographically distributed engineering teams and collaborate with external subcontracting partners, managing schedules, risks, dependencies, and resource allocation across sites
• Interface directly with customers, internal management, Sales, IP and EDA business units, and to align on technical decisions, delivery milestones, and tapeout readiness
• Conduct technical reviews and make major design decisions that balance performance, power, area, quality, schedule, and cost targets for multi‑billion transistor designs at advanced process nodes
• Support technical presales by gathering requirements and preparing effort estimates

The Impact You Will Have

• Expand Synopsys’ EDA and IP business by providing technical leadership for turnkey design engagements
• Deliver first‑pass silicon success on complex SoCs that power AI, automotive, HPC, networking, and datacenter products used by customers worldwide
• Enable faster time‑to‑market for Synopsys customers by defining implementation strategies and methodologies that reduce risk and accelerate tapeout schedules
• Reduce costly respins and schedule delays by catching critical design, timing, and signoff issues early through disciplined review processes and quality metrics
• Strengthen customer relationships and satisfaction by delivering on commitments, managing expectations transparently, and solving technical challenges that matter to their roadmaps

What You’ll Need

• Master's degree in Electrical Engineering, Computer Engineering, or related discipline
• 15+ years of semiconductor industry experience with proven leadership of complex SoC or ASIC projects through successful tapeout
• Extensive hands‑on expertise in both SoC front-end and back-end implementation.
• Deep knowledge of SoC architecture and integration, RTL design in Verilog/SystemVerilog, functional verification, DFT, physical design and implementation, timing signoff constraints, and timing closure methodologies.
• Strong experience with advanced process nodes and the implementation challenges that come with them, including managing IR-drop, EM, and multi-corner multi-mode timing closure
• Direct experience integrating and hardening high-speed subsystems such as PCIe, DDR, UCIe, or Ethernet in SoC environments
• Proficiency with Synopsys EDA tools including Fusion Compiler, PrimeTime, PrimePower, VCS, Formality, Redhawk SC, TestMax, and VC Spyglass; experience with Platform Architect, DSO.ai, Fusion.ai, RTLA, TCM, or Git/GitHub/Copilot is a plus
• Experience with multi‑billion transistor SoCs, chiplet‑based architectures, advanced packaging, AI/ML, automotive, HPC, networking, or datacenter products, or functional safety standards such as ISO 26262 is a plus

Who You Are

• Proactive and self‑motivated, with the ability to take initiative and work independently with minimal guidance.
• Customer‑focused and results‑oriented, with a strong commitment to delivering excellence.
• Collaborative and adaptable, with the ability to thrive in dynamic, fast‑paced environments.
• Detail‑oriented and quality‑driven, with a meticulous approach to achieving high standards of performance.

The Team You’ll Be Part Of

You’ll join the System Solution Group at Synopsys, a customer‑facing expert engineering organization that delivers architecture, RTL, verification, and implementation services, often end‑to‑end, to help customers successfully tape out the most complex SoCs using Synopsys EDA tools and IP.

You’ll collaborate with experts across continents, combining deep technical knowledge with practical delivery, and play a central role in shaping the next generation of silicon products.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings.