Integrated Circuit Design Verification Engineer

• Work as part of a multi-disciplinary team designing display Integrated Circuits for AR
• Work closely with digital design, analog logic, software and verification engineers
• Develop and implement UVM-based and assertion-based testbenches
• Create and execute verification test plans, including functional coverage and code coverage
• Utilize Siemens Questa tool set for verification and debug tasks
• Specify and configure tools and create automation

Requirements

• BSEE or MSEE or relevant years of experience
• 10+ years of experience in ASIC Design Verification
• Strong knowledge of UVM and SystemVerilog for advanced verification methodologies
• Strong knowledge of digital functional simulation, and tools such as Siemens Questa
• Strong knowledge of good Verilog RTL coding practices
• Scripting and automation, such as TCL, Make, Perl, Python and Shell scripts in Linux environment

Hard Skills

• UVM-Based Testbenches
• Assertion-Based Testbenches
• Digital Functional Simulation
• Verilog RTL Coding Practices
• TCL
• Make
• Perl
• Python
• Shell Scripts
• Linux Environment

Certifications & Qualifications

• BSEE
• MSEE