Lead Analog Layout Engineer

We are seeking a highly skilled and experienced Lead Analog IC Layout Engineer to join our dynamic team in Munich and to lead top-level chip planning and perform block-level custom layouts for CMOS and BiCMOS circuits in planar processes. You will be responsible for contractor based in Asia and India and must have previous experience guiding contractors. You will also play a key role in mentoring junior engineers and contribute to the development of standardized layout methodologies. This is an excellent opportunity for a seasoned professional with lead experience and a strong people skills to make a significant impact in a collaborative and innovative environment.

This role is fulltime on site in Munich and applications from across the EU will be considered if the applicant has a pre-existing work permit for Germany. (no visa sponsorship)

As a Lead Analog IC Layout Engineer, your key responsibilities will include:

• Leading top-level chip planning and performing functional-block-level, block-level, sub-block-level, and leaf cell custom layouts for CMOS and BiCMOS circuits
• Conducting schematic-driven layouts and adhering to design constraints
• Designing die-area efficient layouts based on circuit designer requirements
• Performing floor-planning, power line planning, shielding, and device-matching layouts
• Verifying layouts and ensuring compliance with DRC, LVS, and ERC standards
• Contributing to chip-level routing, layout needs, integration, verification, and tape-out processes
• Collaborating with local and global design and layout teams across multiple time zones
• Training and mentoring junior layout engineers and offshore layout contractors
• Developing and implementing standard layout methodologies and workflows across sites
• Building processes and procedures to achieve high-quality layouts
• Supporting additional projects as assigned by management

Qualifications and experience

• Industry degree in Microelectronics Engineering, BSc or higher
• 8+ years of experience in layout design for analog and full-custom digital blocks, IP Layout is not sufficient
• Proficiency in TSMC 65nm, 55nm, 28nm and 22nm process technologies
• Advanced skills in using layout editing tools within the Cadence Virtuoso design environment
• Strong knowledge of debugging DRC/LVS/ERC using Cadence PVS or Mentor Calibre
• Conceptual understanding of layout topics such as parasitics, matching, crosstalk, transistor layout-dependent effects, latch-up, IR drop, electro-migration (EM), and deep N-well and NTN isolation
• Proven ability to solve device matching, electro-migration, signal integrity, and power distribution challenges while adhering to area constraints
• Experience in chip-level floor planning, analog block integration, and tape-out processes