Master Thesis in GPU-Accelerated Implementation and Optimization of a Packet-Level Peeling Decoder

The DLR Institute of Communications and Navigation is dedicated to mission-oriented research in selected areas of communications and navigation. Its work ranges from the theoretical foundations to the demonstration of new procedures and systems in a real environment and is embedded in DLR's Space, Aeronautics, Transport, Security and Digitalization programmes.

What To Expect

The Information Transmission Group was established within the Satellite Networks Department of the Institute of Communications and Navigation to investigate techniques for reliable and secure transmission, processing and storage of information. Grounded on a firm theoretical background, we target the development of algorithms for satellite and (more generally) for wireless communication systems, with emphasis on forward error correction schemes, physical layer techniques and (massive) multiple access. Specific application areas of interest are currently satellite/cellular IoT systems, high-throughput wireless links (including free-space optical communications), as well as high-mobility channels and reliable processing and storage of information.

Your tasks

This position (Master Thesis or Internship) focuses on the software implementation of a packet-level peeling decoder. The main objective is to deploy and optimize the decoder on a modern computing platform combining an ARM-based CPU and an NVIDIA GPU (CUDA, e.g., NVIDIA DGX). The focus is not on mathematical coding theory, but on pure programming implementation to achieve high data throughput. The tasks involve writing clean and performant C code, experimenting with parallel computing via CUDA kernels, and handling efficient memory/cache management. The candidate is expected to work with a high degree of self-reliance on the practical software development.

Your profile

• Advanced and solid programming skills in C/C++.
• Strong interest in parallel computing (CUDA) and/or low-level software optimization.
• Basic understanding of memory hierarchies or cache management is beneficial (a background in CUDA or ARM SIMD/Neon Intrinsics is a plus, but not mandatory).
• High degree of self-reliance, proactivity, and dependability.
• Proficiency in English; a general background in telecommunications or networking is welcome, but not strictly required.