Principal Engineer Digital Design (f/m/div)

In this role you will lead the architectural and implementation work on automotive digital IPs within Infineon’s R&D team, shaping complex clocking, reset, and power-management blocks. You collaborate with cross-functional groups to ensure safe, high-performance designs that meet ISO 26262 and project goals. You drive reusable IP development and guide a design team through verification, timing, and safety integration. This is a mission-driven opportunity to advance automotive silicon at scale and impact real-world mobility and energy solutions.

• Architectural and concept development for automotive IPs, focusing on system resources like clocking and reset
• Design, RTL coding, synthesis, and integration of digital/mixed-signal blocks
• Analyze digital blocks for corner cases and performance
• Own microarchitecture design, specification, and maintenance
• Perform static timing analysis and optimize power/area/performance in collaboration with physical design
• Coordinate with verification teams for block- and system-level validation
• Ensure designs comply with ISO 26262 and implement safety mechanisms
• Identify and mitigate technical risks in timing, design, and functionality
• Advance scalable, reusable IP development to meet platform needs
• Lead a design team and work with cross-functional groups for seamless integration

• 8+ years in digital design with automotive and safety-critical focus
• Expertise in RTL using SystemVerilog, Verilog, and VHDL
• Knowledge of low-power design techniques across multi-power/multi-clock/multi-reset domains
• Experience with synthesis, STA, and power/performance trade-offs
• Familiarity with debug tools and simulation/emulation methods
• Understanding of ISO 26262 and safety mechanism implementation is a plus
• Strong problem-solving and independent working capability
• Excellent cross-team communication in English
• Familiarity with infrastructure IPs and system-level design requirements
• Experience with DFT (Design for Test)

• strong problem-solving
• excellent communication
• team leadership
• RTL coding: SystemVerilog/Verilog/VHDL
• low-power design techniques
• synthesis and static timing analysis (STA)