Senior Digital ASIC Design Engineer Synthesis (m/f/d)

Aufgabe

Job Duties & Responsibilities

• Architecture development for CMOS designs
• Design and RTL coding of digital and full‑custom modules
• Verification on module and chip level, including test plan/cases generation
• Documentation of implemented functionality
• Constraint generation and synthesis of IP blocks and the chip top level
• Analysis of timing and power consumption
• Support for floor‑planning and physical design
• Close collaboration with design partners

Qualifikation

• University degree, Diploma or BS in EE
• Background in digital design (SOC) and ASIC design methodologies
• Experience in silicon development cycle, RTL coding in Verilog and SystemVerilog
• Experience with standard simulation tools for digital designs
• Basic knowledge of UNIX or Linux environments and programming languages
• Technical communication, teamwork, and problem‑solving skills
• English language skills

Location : Böblingen

Senior Digital ASIC Design Engineer – Synthesis (m/f/d)