Senior Digital Design Verification Engineer (d/m/f)

In this role you drive verification strategy for digital and mixed-signal IPs, shaping testbench architecture and verification plans. You collaborate with design colleagues to extract features and ensure high coverage with reusable verification environments. You apply advanced methods (UVM, Formal Verification) to build scalable testbenches and automate verification tasks. You will also mentor junior engineers and communicate project status with customers and stakeholders. This position offers hands-on impact in verification at system and IP levels in a fast-paced environment.

• Define verification strategy for digital and mixed-signal IPs per system requirements
• Define testbench architecture and partition, develop verification plan, collaborate with design engineers
• Apply UVM, Formal Verification and build reusable verification environments and components
• Develop IP-level and system-level testbenches with maximum coverage and reuse
• Create constraint random tests, checkers, and coverage models based on IC specs
• Define infrastructure to support mixed-signal verification and analog/real-number modeling
• Execute verification plans: environment setup, RTL/gate-level regressions, coverage collection, debug
• Communicate with customers/marketing and other work packages; present in design reviews and track schedules
• Mentor junior engineers and share knowledge through project work

• Emphasis in Digital Verification; 7+ years with Master’s or 10+ years with Bachelor’s
• Expertise in digital verification including testbench architecture and verification planning
• Experience with IPs (block-level) and integrated systems verification with reusable components and coverage models
• SystemVerilog for verification (UVM, SVA or similar) including constrained random and metric driven verification
• Experience in Formal verification
• Experience with EDA tools used for simulation, regressions, feature extraction and verification planning
• Ability to set up and automate verification tasks (plus)
• SystemVerilog RNM and analog behavioral modelling
• Familiarity with digital/analog flows and scripting (Python, Tcl, Perl) for automation
• English fluency
• Excellent teamwork, calm professional demeanor, good listening and prioritization skills

• team player
• calm professional demeanor
• excellent listening skills
• SystemVerilog (UVM, SVA or similar)
• Constrained random verification
• Metric driven verification