Senior Digital Verification Engineer

Position: Senior Digital Verification Engineer

Location: Braunschweig, Germany

About the client

They offer an exciting high‑tech opportunity in a growing business environment at an internationally‑minded market leader in the field of high‑speed optoelectronic components. You will find a creative and productive work atmosphere and flexible work environment with a lot of room for career advancement that shares the desire to succeed and a fascination for technical challenges and technological progress.

Responsibilities

• Develop verification specifications and plans for complex SoCs
• Lead verification efforts on module, cluster and top‑level
• Implement UVM environments for functional, netlist and power simulations
• Develop reusable verification IP using the UVM framework
• Develop reference models using System Verilog / Matlab / Python
• Improve verification flow and methodology
• Debug design modules using state‑of‑the‑art simulation and formal tool and methods
• Collaborate with system engineers on post‑silicon debug and device bring‑up in the lab

Qualifications

• Master’s degree (Dipl.-Ing.) or PhD in electrical engineering or computer science
• Minimum 10 years of experience in verification of complex SoC designs
• Excellent programming skills in System Verilog and SVA
• Excellent knowledge of metric-driven verification methodology and flow
• Broad expertise in development of SV/UVM environments for complex SoCs
• Excellent knowledge of state‑of‑the‑art simulation and formal tools (Cadence/Synopsys)
• Good programming skills in Matlab, Python, Perl
• Application knowledge in optical communication systems or optical DSP architectures would be a plus
• Expertise in real‑number modelling (RNM) of analog circuits would be a plus
• Excellent written and verbal communication skills in English both internal and client‑facing
• Good language skills in German would be a plus
• Willingness to travel occasionally