Senior Formal Verification Engineer – Vector Unit

Responsibilities

• Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks
• Implement advanced word-level modeling, bit‑blasting, and algebraic rewriting strategies
• Independently diagnose and resolve proof‑convergence failures, over‑constraints, and state‑space explosions
• Develop formal environments to mathematically prove compliance with the RISC‑V Vector Extension specification
• Collaborate closely with simulation engineers to ensure maximum bug‑hunting efficiency

Requirements

• B.S./M.S. in Computer Engineering, Electrical Engineering, or Computer Science; or a Ph.D. in formal methods or computer arithmetic
• 5+ years of production‑grade hardware verification experience (or Ph.D. + 1–3 years)
• Strong specialization in arithmetic formal verification, algebraic rewriting, and word-level modeling
• Good working knowledge of high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware
• Proficient command of commercial EDA formal tools (e.g., Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin)
• Native fluency in SystemVerilog and SVA; scripting proficiency (Python, Tcl, or Bash)

Core Competencies

Demonstrates expertise in formal verification environments, particularly for Vector Unit sub-blocks, with a strong focus on arithmetic formal verification and compliance with RISC-V Vector Extension specifications. Proficient in using commercial EDA formal tools and scripting languages to enhance verification processes.

Tools & Technologies

• Cadence JasperGold
• Synopsys VC Formal
• Siemens OneSpin
• Python
• Tcl
• Bash