Senior High-Speed Analog/RF System Architect (f/m/d)

As Senior Analog/RF System Architect, you own the analog, RF, and high-speed SerDes architecture of CMOS SoCs for graphene photonic interconnects. You define the electrical boundary between electronics and photonics and drive architecture decisions across the full electrical-to-optical channel. You work with cross-functional teams to translate deployment needs into scalable, manufacturable solutions and assess ROI for future features. This role offers impact at the intersection of electronics and photonics, shaping next-generation, energy-efficient interconnects.

• comprehensive benefits package
• outstanding insurance
• pension
• virtual stock options
• focus on work-life harmony
• professional and personal development

• Own analog/RF and high-speed SerDes architecture for optical transceiver SoCs (drivers, TIAs, equalizers, ADC/DACs, PLLs, CDRs) for 112G/224G+ PAM4 and beyond
• Define and maintain Analog Product Requirement Specifications (PRS) including architecture, verification plans, and PPA estimates
• Drive system-level link budget closure across the electrical-to-optical channel
• Own the Analog IP roadmap and align with technology capabilities, EDA flows, and external design partnerships
• Collaborate with Photonics Circuit Designer, Package Electrical/SI Architect, and SoC teams to reconcile analog/RF architecture with PIC layout and constraints
• Define Customer Requirement Documents (CRDs) and engage with customers to ensure deployment requirements are met
• Lead SoC concept and feasibility studies, evaluating architectural options and ROI for features
• Track interconnect standards (PCIe, UCIe, CXL) and their impact on architecture

• Ph.D. in Electrical Engineering or related field with 5+ years of relevant experience, or Master’s with 8+ years
• Proven experience owning high-speed SerDes and analog/mixed-signal architectures (PLLs, TIAs, drivers, equalizers, ADC/DACs, CDRs) for 56G/112G/224G+ PAM4 in advanced CMOS (FinFET/GAA)
• Strong system-level architecture experience from concept to sign-off, including advanced packaging (2.5D/3D)
• Expertise in electrical-optical link budget analysis (transmitter impairments, channel loss, crosstalk, receiver noise)
• Hands-on characterization of high-speed analog/RF designs with BERTs, oscilloscopes, VNAs
• Solid understanding of PCIe, UCIe, and CXL and their influence on analog/RF decisions
• Ability to collaborate across photonics, packaging, digital, product, and customer teams
• Strong technical communication skills for translating deployment requirements into specs
• Experience with Cadence Virtuoso/Spectre, MATLAB/Simulink, Keysight ADS, HSPICE, Ansys HFSS/SIwave, Python-based workflows

• strong communication
• cross-functional collaboration
• customer-facing engagement
• SerDes architecture
• analog/mixed-signal design
• PLL/CP/Driver/TA/Equalizer/ADC/DAC design