Senior Staff Engineer Digital Verification (f/m/div)

In this role you shape verification strategy for digital and mixed-signal designs, work closely with architects and cross-functional teams, and lead verification engineers to deliver robust RTL and gate-level tests. You will mentor juniors, advance verification methodologies, and collaborate on scalable flows that support Infineon’s green and secure technology leadership. This is a hands-on, impact-driven position at the intersection of creativity and engineering excellence.

• competitive salary
• additional benefits
• salary paid 14 times per year
• higher compensation based on expertise
• collective wage agreement
• equal opportunity

• Create and define verification plans for digital or digital mixed signal designs
• Develop and enhance verification environments in SystemVerilog/UVM
• Write and execute tests for RTL and gate-level
• Debug design and verification issues
• Lead and coordinate other verification engineers
• Collaborate with architects, designers and other verification engineers
• Mentoring of junior colleagues, consultants and students
• Contribute to improvement of existing methodologies and flows

• University degree in Electrical Engineering, Information Technology, Telematics, or related field with focus on electronics
• At least 6 years of professional experience in digital verification; technical leadership desirable
• Expert knowledge of SystemVerilog and UVM; solid understanding of SystemVerilog for design
• Strong scripting skills (bash, tcsh, Python, TCL)
• Knowledge of formal verification and mixed signal verification is an advantage
• Fluent English; German skills a plus

• leadership
• mentoring
• cross-functional collaboration
• SystemVerilog
• UVM
• RTL and gate-level testing