Senior Staff- Interface IP Verification (Pre-Silicon- PCIe/CXL/DDR/Ethernet)

In this role you will lead end-to-end verification of Interface IP blocks (PCIe, CXL, DDR, Ethernet) before tape-out, ensuring robust pre-silicon validation. You will build reusable, scalable UVM-based testbenches and define effective verification strategies to cover system-level integration and protocol compliance. You will collaborate with architecture, design, firmware, and systems teams, mentoring colleagues and shaping verification methodology. This position offers impact across AI, data-center, and automotive silicon via high-quality IP that powers next-gen platforms.

• Own end-to-end verification of Interface IP blocks from architecture review to silicon signoff
• Build and evolve reusable UVM-based verification environments across product lines
• Define verification strategies and test plans for protocol compliance and system integration
• Develop constrained-random, coverage-driven test scenarios using SystemVerilog and UVM
• Debug multi-layer issues across RTL, timing, and testbench infrastructure with industry simulators
• Collaborate with architecture, design, firmware, and systems teams to resolve issues early
• Mentor verification engineers on UVM methodology, coverage analysis, and best practices

• 8+ years of hands-on ASIC/SoC verification experience
• Deep expertise in SystemVerilog and UVM, with scalable verification environment experience
• Strong protocol knowledge in PCIe, CXL, DDR, or Ethernet and ability to translate specs into verification requirements
• Proven experience with constrained-random and coverage-driven verification
• Solid debugging skills across RTL, verification infrastructure, and protocol compliance
• Experience with simulators such as VCS or ModelSim
• Experience with verification IP development, assertion-based verification, or formal methods is a plus
• Knowledge of modern SoC architectures and high-speed interfaces is a plus

• Mentorship and leadership
• Strong collaboration across cross-functional teams
• Problem-solving under tight schedules (2 a.m. regression triage)
• SystemVerilog
• UVM
• constrained-random testing