Staff Engineer Physical Verification Methodologies (f/m/div)

Your Role

Key responsibilities in your new role

• Collaborate with technology specialists to establish advanced physical verification and parasitic extraction methodologies
• PDK and design team support for developing automated checks in electrical, ESD, reliability verification, and parasitic extraction
• Collaborate closely with physical implementation teams and support the design departments with your expert knowledge on EDA tools, flow, and methodology
• Analyze existing and new CAD software solutions in cooperation with the design flow development team
• Provide specification documents and training as part of the design flow and methodology development
• Lead and implement Calibre DRC, ERC, LVS, and PERC Physical Verification runsets in-house and external wafer technologies

Your Profile

Qualifications And Skills To Help You Succeed

• A university degree in Electrical Engineering, Physics, Microelectronics/Semiconductor Technology, Computer Engineering or Computer Science; a PhD is preferred, or similar/equivalent experience
• At least 3-5 years of hands‑on experience with leading EDA tools (e.g., StarRC, Quantus, Genus, Innovus, Design, FC, and Calibre)
• Experience in working with EDA vendors to resolve tool issues
• Strong scripting skills in at least two of the following: Python, Tcl, PERC, SVRF, Skill
• Understanding of semiconductor device physics and multi‑domain design
• Proactive mindset, good communication skills for stakeholder management, and ability to bridge customer needs into requirements
• Excellent English skills; German is beneficial

Contact

Theresa Albrecht

Equal Employment Opportunity Statement

We base our recruiting decisions on the applicant´s experience and skills. We are committed to giving all applicants and employees equal opportunities.