Senior Functional Verification Engineer

Senior Functional Verification Engineer

Location: Mannheim, Germany (Hybrid) or Villach, Austria (Hybrid)

Salary: Negotiable

Duration: Permanent

About the Role

We’re looking for a Senior Functional Verification Engineer to join a high‑performing Functional Verification Team developing and verifying state‑of‑the‑art on‑chip network (NoC) solutions. This position offers the opportunity to work on complex, high‑impact projects with a strong focus on design quality, timely delivery, and customer‑oriented innovation.

Key Responsibilities

• Develop and maintain UVM SystemVerilog verification environments for NoC IP.
• Define and execute comprehensive verification plans aligned with design and product specifications.
• Design, implement, and continuously enhance verification testbenches.
• Debug and analyze functional issues, ensuring high reliability and performance.
• Drive coverage closure and monitor daily regression results.
• Collaborate closely with digital design and cross‑functional teams to ensure successful, on‑time product releases.

Your Profile

• B.S. or M.S. in Electrical Engineering, Computer Engineering, Physics, Information Technology, or a related field (with emphasis on hardware design).
• Minimum 5 years (including internships) in functional verification or related roles.
• Strong knowledge of UVM SystemVerilog and SystemVerilog Assertions.
• Experience with Cadence Xcelium and vManager preferred.
• Familiarity with HDL coding is a plus.
• Scripting experience in Python, TCL, or Bash is advantageous.
• Knowledge of Specman‑e is a plus.
• Strong problem‑solving attitude and hands‑on approach.
• Excellent communication skills in English (German is an advantage).

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