Principal AMS Verification Engineer

Stellenbeschreibung:

Are you excited about R&D? An R&D Centre in Munich is looking for an experienced AMS Verification Engineer to work full time in their office (no hybrid working!). International candidates with strong skills in System C, System Verilog, Verilog A will be considered and visa can be provided for an exceptional candidate. A competitive salary package including a bonus will be offered.

Responsibilities

System level model development for analog/mixed signal ASIC/IP according to both application and circuit design requirements
Implementation of user cases, fault injection and simulation test bench for analog system design verification
Maintenance and quality assurance for analog system models’ accuracy, scalability and reusability
Work with CAD group to improve the mixed signal verification methodology
Analog/ mixed signal fault modeling and simulation

Requirements

Successfully completed Master or PhD. degree in Electrical Engineering, Microelectronics or any related fields of study and ideally experience in an R&D environment
Industry experience in analog/ mixed signal behavior modeling ( System C, System verilog, Verilog A)
Knowledge or hands-on experience in analog/mixed circuit design ( LDO, Buck, ADC, PLL)
Experience of analog/mixed signal design verification

For more information and to apply, please contact Molly with your CV and a time for an initial call.