Compiler Engineer - Heuristics, PNR Tool & FPGA/CGRA

We are looking for a Compiler Engineer who will develop new heuristics for a place-and-route tool and take over its overall maintenance and integration. Focus areas include, but are not limited to: Design and implementation of heuristics based on feedback from our application engineers; taking over the ongoing maintenance and improvement of the tool; integration of an externally developed optimal solver.

Prospective team members require strong C++ skills and a solid grounding in graph algorithms and optimisation ; experience with Python or similar scripting languages; interest in or exposure to EDA / place-and-route, CGRA, FPGA, or compiler back-end mapping . Familiarity with ILP solvers is a plus.

Master’s degree (or equivalent experience) and first relevant experience (internships, projects) welcome.

Relocation required. Currently 4 days on-site, 1 day remote. Policy may change.