Senior RTL Engineer, Interconnect Design

About the Team

OpenAI’s Hardware organization develops silicon and system‑level solutions designed for the unique demands of advanced AI workloads. The team is building next‑generation AI‑native silicon and infrastructure to support large‑scale training and inference systems. Within Hardware, the SoC design team works across architecture, RTL design, verification, physical design, performance, firmware, and systems engineering to deliver production‑quality silicon for OpenAI’s supercomputing infrastructure.

About the Role

We are looking for a highly experienced RTL engineer to own critical on‑and off‑chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on‑chip communication fabrics connecting high‑bandwidth compute, memory, and I/O subsystems as well as purpose‑built off‑chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands‑on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure.