Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)

In this role you will lead pre-silicon verification of Interface IP (PCIe, CXL, DDR, Ethernet) at Synopsys, ensuring robust signoff before tape-out. You will build reusable UVM-based testbenches and drive end-to-end verification from architecture reviews to silicon qualification. You will collaborate across architecture, design, firmware, and systems teams to catch protocol issues early and guide verification strategy. This is a hands-on, leadership-focused position that shapes IP quality for AI platforms, cloud infrastructure, and data-center systems. You will mentor engineers, raise verification standards, and influence early design decisions to improve efficiency and robustness.

• health benefits
• wellness programs
• financial benefits

• Own end-to-end verification of Interface IP blocks from architecture review to silicon signoff
• Build and evolve UVM-based verification environments reusable across product lines
• Define verification strategies and test plans for protocol compliance and system-level integration
• Develop constrained-random, coverage-driven test scenarios targeting functional coverage and signoff quality
• Debug multi-layer issues across RTL, timing, and testbench infrastructure using simulators (e.g., VCS)
• Collaborate with architecture, design, firmware, and systems teams to resolve issues early
• Mentor verification engineers on UVM methodology, coverage analysis, debugging techniques, and best practices

• 8+ years of hands-on ASIC/SoC verification experience
• Deep expertise in SystemVerilog and UVM with scalable verification environments
• Strong protocol knowledge in PCIe, CXL, DDR, or Ethernet
• Proven experience with constrained-random and coverage-driven verification for functional signoff
• Solid debugging across RTL, verification infra, and protocol compliance
• Experience with simulators like VCS or ModelSim
• Verification IP development, assertion-based verification, or formal methods is a plus
• Knowledge of modern SoC architectures and high-speed interfaces is a plus

• leadership and mentorship
• strong communication
• problem-solving under pressure
• SystemVerilog
• UVM
• constrained-random verification