Design for Test Engineer (m/f/d) - REF84987L

Job Description

As a DFT engineer (m/f/diverse) for Continental ASICs, you will define and implement DFT (Design for Test) and BIST (Built-In Self-Test) concepts. You will develop DFT specifications and drive DFT architecture and methods for designs and IPs to maximize test coverage while minimizing costs.

You will have the opportunity to work on Continental’s diverse automotive applications and develop optimized solutions tailored to their specific needs. Special care must be taken to meet the stringent automotive requirements.

Your responsibilities will include:

1. Defining and implementing DFT and BIST concepts and IPs to enhance test coverage and cost efficiency.
2. Developing scripts for automatic scan insertion and executing scan insertion and ATPG (Automatic Test Pattern Generation).
3. Performing test coverage analysis and implementing improvements.
4. Leading and managing SOC Design for Test efforts on complex projects, ensuring coverage, manufacturability, and quality standards are met.
5. Developing full chip and block-level DFT implementations based on specifications and quality goals.
6. Innovating and enhancing DFT methodologies for Continental.
7. Collaborating closely with chip design, semiconductor manufacturing, and related teams.
8. Implementing and verifying testability features in System-on-Chip designs.
9. Creating and simulating test patterns for production testing.
10. Developing DFT specifications and driving flow and methodology improvements.
11. Implementing and validating DFT structures such as LBIST, MBIST, IP tests, Scan, and compression.
12. Providing technical guidance to other DFT engineers and related teams.
13. Supporting pattern delivery to post-silicon test engineering teams, ensuring compatibility with tester requirements.
14. Working with cross-functional teams to define DFT strategy, verification, and automation.
15. Contributing to development early feedback to concept, architecture, and design teams.
16. Improving DFT process flows and methodologies continuously.
17. Collaborating during test planning, pre-silicon verification, and post-silicon validation.
18. Working with IP test development teams to define test schemes and implementation styles.

Qualifications

• Academic degree in Electrical Engineering, Microelectronics, Physics, or a comparable qualification.
• Extensive relevant work experience.
• Proven expertise in DFT engineering with a record of innovation.
• Experience in developing DFT specifications and architecture.
• Knowledge of industrial standards such as ATPG, JTAG, MBIST, and trade-offs in test quality and time.
• Proficiency in SystemVerilog RTL, TCL, Python, and Unix/Linux environments.
• Familiarity with Siemens, Cadence, and Synopsys DFT tools.
• Excellent English language skills (written and spoken).
• Strong communication, negotiation, and teamwork skills.
• Customer-focused with proactive needs anticipation.
• Motivated, dynamic, and operates with integrity.

Applications from severely handicapped individuals are welcome.

Additional Information

Are you ready to advance your career and be part of something big? Apply now and join AUMOVIO to shape the future of mobility!

Take your career to the next level with us at the forefront of innovation. Apply now to become part of AUMOVIO and drive future mobility!

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