Digital Verification Engineer (Specman) – Semiconductor (all gender)

Stellenbeschreibung:

Digital Verification Engineer (Specman) – Semiconductor (all gender)

As one of the world's leading engineering service providers, we at ALTEN are committed to positively shaping the future of our partners, the careers of our employees and the challenges facing our society and environment.

Job Description

Verify mixed‑signal designs on block and system level resting upon formal and functional verification
Interpret product requirements to create the verification concept and the product verification specification
Perform random‑constraint testbenches according to the state of the art
Create assertions to prove the design using formal methods
Work in collaboration with lab and test engineers, designers, system architects, and verification engineers across multiple sites

Qualifications

Have completed an engineering degree in electrical engineering, computer science or similar studies
Already have practical experience in the field of digital functional verification and common safety standards
Have extensive programming skills in coding in System Verilog and System Verilog assertions
Have good knowledge of UVM methodology and Specman‑e language, scripting languages like Python or Perl, and ability to interpret RTL and gate‑level code
Have good communication skills in English

We value diversity and therefore welcome all applications – regardless of gender, nationality, ethnic and social origin, religion/belief, disability, age and sexual orientation and identity. Severely disabled persons will be given preferential consideration if they are equally qualified.