Electronic-Photonics IC Mask Data Preparation & GDS Data Integration Engineer

The Role

We are seeking an experienced Electronic-Photonics IC Mask Data Preparation & GDS Data Integration – SMTS to take technical ownership of the complete tape‑out flow — from GDS database integration and mask data preparation through mask release, first silicon bring‑up, and post‑tapeout support.

In this role, you will drive EIC+PIC DfX co‑integration (Design for Functionality, Manufacturing, Test, Packaging, and Reliability) across a 300 mm graphene photonics platform, ensuring seamless alignment between design, fabrication, testing, and packaging requirements throughout the development cycle.

Responsibilities

• Own the complete tape‑out flow including Mask GDS/MDP integration, DRC/LVS/ERC verification, final mask sign‑off, and rule file maintenance for PIC‑EIC integration and new process nodes.
• Lead GDS and reticle‑to‑fab delivery, formal mask release activities, and ensure all layers, formats, and data structures comply with fab specifications.
• Drive DFM and DFT integration through yield optimization, hotspot mitigation, layout optimization, and implementation of scan chains, test pads, and optical probe structures within GDS.
• Design and integrate special GDS structures including kerf, seal ring, frame, scanner marks, metrology & PCM structures, ESD protection layouts, and RDL packaging interfaces.
• Act as the primary interface between mask shops, foundry lithography/metrology teams, EDA vendors, and cross‑functional analog, digital, packaging, and reliability teams across global regions.
• Maintain GDS version control and audit‑trail archiving while supporting first‑silicon debug, layout‑based failure analysis, and continuous improvement of MDP best practices.

Qualifications

• MS or PhD in Electrical Engineering, Physics, or a related field, with 5+ years of experience in semiconductor or photonics tape‑out, layout integration, and Mask Data Preparation (MDP).
• Strong expertise in GDSII/OASIS, DRC/LVS/ERC verification flows, and industry‑standard tools such as Calibre and Synopsys ICV, including MDP job deck authoring and JDV (Jobdeck View).
• Hands‑on experience with production tape‑out flows including DFM, DFT, ESD, seal ring/kerf, and RDL layout implementation.
• Familiarity with OPC flows for advanced photonics or CMOS nodes and experience coordinating with mask shops and foundry partners.
• Experience with Photonic IC technologies (Si, SiN, etc.), graphene or 2D‑material integration, RF photonics, or photonic/electronic co‑design EDA tools such as Cadence EPIC or Lumerical is considered a plus.
• Background in mask shops or EDA software environments (e.g. Synopsys, Siemens, Cadence, Toppan, Photronics, Compugraphics, Tekscend) is highly desirable.

Benefits

Your health and future matter. We offer a comprehensive benefits package with outstanding insurance, pension and virtual stock options for your mental, physical, and financial health.