Principal Engineer Design

In this role you will own end-to-end IO library design and development, collaborating with system architects to define specifications. You will guide IO integration into subsystems, qualify IO choices, and drive quality sign-offs aligned with project milestones. You’ll shape IO architectures to meet product requirements while mentoring the team to optimize design performance, power, and area. This position offers hands-on FE/BE support and opportunities to advance verification methodologies, contributing to Infineon’s mission of greener, smarter solutions.

• Own end-to-end IO library design and development
• Collaborate with system architects to define and finalize IO specifications
• Lead IO integration into subsystems and provide expert guidance on IO selection, implementation, and qualification
• Drive IO quality sign-offs and ensure compliance with milestone deliverables
• Define IO architectures and align designs with product requirements
• Mentor and review team members' work to improve design quality, performance, power, and area optimization
• Provide hands-on support for Front-End (FE) and Back-End (BE) development activities
• Enhance design and verification methodologies to improve efficiency and quality
• Ensure adherence to quality standards and development processes for library design

• BE/BTech/MTech in ECE, VLSI, or related field with 12+ years of IO design and development experience
• Strong expertise in IO design for LVTTL, LVCMOS, DDR, SPI, xSPI, Oscillator, LVDS, and voltage-tolerant circuits
• Good understanding of ESD and Latch-Up concepts
• Experience with IO library characterization methodologies
• Proven ability to lead small design/layout teams and drive architecture development and project planning
• Track record of delivering chip designs from specification to silicon
• Strong process management, problem-solving, multitasking, and attention to detail
• Excellent analytical, communication, and cross-functional collaboration skills

• excellent analytical skills
• clear communication
• cross-functional collaboration
• IO design for LVTTL, LVCMOS, DDR, SPI, xSPI, Oscillator, LVDS
• voltage-tolerant circuits
• ESD and latch-up awareness