Senior Hardware Compute Architect (f/m/d)

As Senior Hardware Compute Architect, you will own the hardware architecture for a hybrid electronic-photonic compute engine. You will design the compute architecture, memory hierarchy, data fabric, and interfaces to enable cross-domain workload execution. You’ll partner with architecture, photonics, and software teams to balance performance, power, area, and manufacturability ahead of silicon. This role blends compute- and interconnect-focused decisions to enable a new class of heterogeneous systems. You’ll contribute to a mission-driven, human-centric culture that aims to redefine chip-to-chip connectivity.

• comprehensive benefits package
• outstanding insurance
• pension
• virtual stock options

• Define hardware architecture for a hybrid compute engine (execution units, memory hierarchy, interfaces)
• Architect system data fabric and interconnects (bandwidth, latency, coherency, die-to-die)
• Collaborate with software and photonics teams to map workloads to electronic vs photonic paths
• Evaluate architectural options using performance/power/area modeling to guide silicon implementation
• Translate compute primitives into implementable system-level architectures across RTL, physical design, and packaging
• Own the hardware architecture specification and sign-off processes

• 5+ years designing compute hardware architecture at the SoC or system level
• Deep expertise in execution units, memory hierarchy, and system-level trade-offs
• Experience with high-performance interconnects and heterogeneous compute systems
• Proficiency in architecture modeling and quantitative analysis (performance, power, area, scalability)
• Experience collaborating with hardware and software teams to define interfaces and requirements
• Experience with architecture modeling/simulation tools and interconnect protocols (CXL, UCIe, NVLink-class, UALink; Python, C++, SystemC)
• Familiarity with photonic/optical compute concepts; experience with GPUs/DPUs/FPGAs or AI accelerators is a plus
• Experience contributing to interconnect standards (CXL/UCIe/UALink) is a plus

• cross-functional collaboration
• communication across hardware and software teams
• structured problem solving
• execution units (scalar, vector, tensor); memory hierarchy; memory tiering
• system interconnects and data fabrics; UCIe, CXL, UALink, NVLink-class
• architecture modeling and simulation tools; performance/power modeling