Advanced Packaging Electrical / Signal Integrity Architect (f/m/d)

In this role you own electrical characterization and signoff for advanced semiconductor packages, building RLGC/2.5D/3D models and leading SI/PI analyses. You work with ASIC/SerDes teams to ensure electrical targets are met while enabling next-generation chiplet and package technologies. You will validate models against measurements and collaborate across package, ASIC, and OSAT partners. The role sits at the intersection of packaging, high-speed design, and simulation-driven co-design, contributing to scalable, energy-efficient interconnect solutions.

• comprehensive benefits package
• outstanding insurance
• pension
• virtual stock options

• Own electrical characterization and signoff for advanced packages (SI/PI, crosstalk, EMI/EMC)
• Develop and validate package-level electrical models (RLGC, S-parameters) for 2.5D/3D, interposers, fan-out, and chiplets
• Define package stack-ups, substrate routing, via strategies, and bump-map/ball-out architectures with cross-functional teams
• Build and correlate simulation models with laboratory measurements to support signoff and end-to-end channel performance
• Support chip-package-board co-simulation and end-to-end channel budgeting with ASIC, SerDes, and system engineering
• Collaborate with OSAT and foundry partners for robust electrical performance, manufacturability, and DFM compliance
• Prepare and interpret SI/PI analysis, and ensure electrical targets align with reliability and thermal constraints

• Bachelor's or Master's in Electrical Engineering, Electronics Engineering, Physics, or related field
• 6+ years in package/PCB SI/PI, high-speed interconnect, or advanced packaging hardware roles
• Strong expertise in transmission line theory, electromagnetics, S-parameters, and channel modeling
• Hands-on experience with SI/PI tools: Ansys HFSS/SIwave, Cadence Sigrity, Keysight ADS, HSPICE
• Experience correlating simulation with measurements using VNA, TDR, oscilloscopes
• Knowledge of 2.5D/3D integration, interposers, fan-out packaging, chiplets, high-density substrates
• Scripting/automation in Python, Perl, Tcl, Cadence SKILL; plus for CEM/DFM tooling is a plus
• Experience with EIC-to-PIC interfaces, UCIe-class interconnects, or standards bodies (IEEE/OIF/JECED) a plus
• Experience with OSAT collaboration on electrical qualification, manufacturing, or DFM a plus

• Cross-functional collaboration
• Strong communication with ASIC, SerDes, and system teams
• Problem solving and analytical mindset
• RLGC and S-parameter modeling
• Package-level electrical/EMC analysis
• 2.5D/3D packaging concepts (interposers, chiplets)