Principal Engineer System Compute (f/m/div)

As Principal Engineer System Compute in Infineon’s R&D, you shape automotive compute architectures and lead HW/SW co-design for high performance, deterministic systems. You’ll drive memory, interconnect, and QoS strategies, plus performance modeling across control, audio, vision, and edge inference workloads. You provide technical leadership across the development lifecycle and translate system needs into concrete, verifiable targets. This role blends deep architecture work with mentoring and cross-functional collaboration, contributing to Infineon’s decarbonization and digitalization initiatives.

• hybrid workplace
• diversity and inclusion
• equal opportunities
• global leader in semiconductor solutions
• career growth and mentoring
• customer- and people-centric culture

• Define compute subsystem architecture for automotive MCUs/MPUs including CPU cores, DSP/vector units, and AI accelerators
• Lead HW/SW co-design with compiler, runtime, firmware, and ML teams to optimize kernels and data movement
• Architect memory hierarchy, DMA, interconnects, and QoS to meet real-time deadlines
• Develop performance modeling and workload characterization for control, audio, vision, and edge inference
• Translate system requirements into specs and targets (PPA/latency/determinism) and drive architectural trade-offs
• Provide technical leadership across development lifecycle, including design reviews, mentoring, roadmap/IP strategy, and stakeholder alignment

• A master’s degree in Electrical Engineering, Computer Engineering, or Computer Science (advanced degree preferred)
• 6+ years in CPU/DSP/NPU architecture/microarchitecture for embedded/edge SoCs; principal-level leadership
• Strong parallel compute expertise (SIMD/vector, multi-core scaling) and deep memory/interconnect knowledge (cache/scratchpad, DMA, coherency, NoC, QoS)
• Hands-on modeling/tools experience (Python, C/C++, analytical models, perf simulators, trace tooling) with ability to develop new methodologies
• Familiarity with real-time determinism and safety concepts (isolation, ECC, functional safety)
• Excellent architecture specification, stakeholder alignment, and mentoring skills
• Fluent English; German a plus

• Mentoring
• Stakeholder alignment
• Communication
• Parallel compute (SIMD/vector, multi-core)
• Memory hierarchy and interconnects (cache, DMA, coherency, NoC, QoS)
• Performance modeling and workload characterization